Ajaya Dahal | FPGA & Systems Engineer

Work Experience

Jan 2023 - Present

Sr. FPGA & Network System Engineer

Advanced Micro Devices, Inc - Remote - Based in Austin, TX

Core Engineering Focus:

• System Engineering: Technical Lead for 15+ Ethernet reference designs (10G – 800G), integrating Hard IP (DCMAC/MRMAC) with DMA subsystems.
• Physical Layer Tuning: Expert in debugging GTY/GTM transceivers, optimizing Eye Diagrams, and resolving signal integrity issues in 400G links.
• Full Stack Integration: Debugging from the RTL (Verilog) up to the OS (PetaLinux/Yocto) and Kernel Drivers.

Lab & Integration Focus

Directed FPGA and digital design labs that bridged reference design HDL, embedded Linux, and lab-based signal integrity tuning for every Ethernet IP from 10M to 800G.

                                        Versal ACAP
                                        Embedded Linux
                                        Signal Integrity
                                    

Hardware & IP Ecosystem:

Versal ACAP: Deep architectural experience with VMK180, VPK120, VCK190. Configuring NoC (Network on Chip) and PL-to-PS AXI interfaces.
Zynq UltraScale+ & RFSoC: ZCU102, ZCU106, and ZCU111/ZCU208 RFSoC (handling high-speed ADCs/DACs).
Ethernet MAC IP:
- 800G/400G: DCMAC (Dual Converter MAC) & MRMAC (Multirate MAC).
- 100G/50G/40G: CMAC (UltraScale+ Hard IP) & Soft 100G cores.
- 10G/25G: 10G/25G Ethernet Subsystem & XXV Ethernet.
- Embedded: PS GEM (Gigabit Ethernet MAC) via EMIO/MIO.

Technical Publications & Knowledge Base:

Authored official AMD Answer Records (ARs) and Technical Blogs to resolve global customer blockers:

📘 MRMAC Tutorial Series

Complete step-by-step guide for building a Versal MRMAC 4x25G Baremetal Ethernet Design from scratch.

AR 000036973 →

                                            Versal ACAP
                                            MRMAC
                                            Tutorial
                                        

🚀 DCMAC Survival Guide

Comprehensive 100G DCMAC reference design for VPK120 with CAUI-4 interface configuration.

AR 000039394 →

⚡ GTY/GTYP Transceiver Latency

Versal GTY/GTYP Transceivers: TX and RX Latency Values for sub-microsecond Ethernet systems.

AR 75868 →

                                            Versal ACAP
                                            SerDes Latency
                                            HFT Critical
                                            Team Contribution
                                        

📚 Additional Technical Publications

AR 000036641 10G/25G High Speed Ethernet Subsystem - Timing closure strategies
AR 000038505 MRMAC Linux Driver - Block Lock Issue resolution
AR 000037069 PS-GTR GEM Driver Patch - Auto-negotiation fixes
AR 000037257 MCDMA Device Tree - Critical device tree modifications for low-latency Ethernet designs

🔬 My Hardware Lab & Active Setups

Versal VCK190

100G Live Traffic Test With MRMAC

XCVC1902 GTM SerDes 100G

Zynq UltraScale+ ZCU111

100G Live Traffic Test with CMAC

XCZU28DR RFSoC 100G CMAC

IBERT Eye Diagram

100G SerDes Tuning Results

Signal Integrity GTY 28 Gbps

Engineering Excellence Awards:

3x25G MRMAC

Happy Customer - Happy FAE

Team Player 2024

AXI 1G/2.5G Ethernet

GEM with TSU via EMIO

QSGMII Default Clock Issue

NA Field Recognition 2025

Customer Excellence

Public Repositories I Maintain:

Versal Ethernet Architecture Zynq MPSoC Ethernet

Aug 2019-Jan 2024

Graduate Research Assistant

Mississippi State University - Starkville, MS

Collaborated with Center for Advanced Vehicular Systems (CAVS) researchers on autonomous vehicle perception systems using LIDAR, radar, and low-cost cameras. Leveraged GPUs and deep learning frameworks (TensorFlow, OpenCV) to detect and track lanes under diverse road conditions. Applied ML techniques like SqueezeSeg for camera-LIDAR sensor fusion. Led multiple SDR-based projects: (1) AI-powered triangulation system to locate contraband cell phones in prisons, (2) spectrum scanning system to detect RF activity using IQ data for passive microwave sensing, and (3) Wi-Fi-based human activity recognition using ML. Selected as 1 of 10 for the MSU/USDA Summer Research Experience. Contributed to 5G research with 5 universities and National Instruments, experimenting with srsLTE/RAN, OAI, and Amarisoft as a Part 107 FAA-certified drone pilot.

SDR & Wireless Sensing Research

Architected real-time RF signal processing systems for contraband detection and human activity recognition, combining software-defined radio with machine learning to push wireless sensing into new applications.

                                        Software Defined Radio
                                        Machine Learning
                                        Spectrum Scanning
                                    

Jan 2020-Jan 2022

PCB Design Engineer Co-op

Hunter Engineering Company - Raymond, MS

Designed system-level functional testers for PCBs used in Hunter Engineering products (e.g., car lifts, wheel balancers, and tire changers). Created end-to-end test systems, including custom PCBs, displays, and interfaces.

Inspection & Process Focus

Standardized visual audits across multiple shifts and partnered with fulfillment teams to document repeat failure modes so corrective actions could be triggered faster.

                                        Visual QA
                                        Root Cause
                                        Shift Handoffs
                                    

to verify board functionality before assembly. Developed intuitive LabVIEW GUIs and C/C++ backend code to ensure ease of use by operators with no technical background, minimizing user error. Integrated camera-based defect detection using OpenCV and built testers compatible with Aegis Factory Logix. Delivered robust, operator-friendly systems that improved quality control and production efficiency.

Engineering Practice

Applied principles from FPGA and digital design courses to architect automated PCB testers, pairing hardware control with embedded software for fast cycle times.

                                        LabVIEW
                                        Embedded Control
                                        Digital Verification
                                    

March 2019-August 2019

Quality Control

Amazon—Woot! Merch by Amazon - Dallas, TX

Ensured quality assurance in a high-volume T-shirt manufacturing facility by inspecting printed garments for accuracy, color consistency, and print defects. Verified customer specifications and maintained production standards. Played a key role in minimizing defective shipments and supporting efficient fulfillment operations.

Inspection & Process Focus

Standardized visual audits across shifts, partnered with fulfillment leads to capture repeat failure modes, and accelerated corrective loops before assembly.

                                            Visual QA
                                            Root Cause
                                            Shift Handoffs
                                        

Education

Academic Journey in Electrical & Computer Engineering

2021 - 2023

Master's in Electrical and Computer Engineering

Mississippi State University Starkville, MS

📄 Master's Thesis

Software Defined Radio (SDR) Based Sensing

This thesis explores Software-Defined Radio (SDR) applications including Spectrum Scanning Systems, Contraband Cellphone Detection, and Human Activity Recognition via Wi-Fi signals. SDRs empower spectrum scanning systems to monitor and analyze radio frequencies in real-time, optimizing spectrum allocation for seamless wireless communication. The research demonstrates SDR-based identification of unauthorized signals in restricted areas and leverages Raspberry Pi 3B+ for tracking movement patterns via Wi-Fi signals. Additionally, a comparative analysis of Wi-Fi-based Human Activity Recognition versus Radar systems was conducted for accuracy assessment, showcasing the versatility of SDR platforms in real-time signal processing and wireless sensing applications.

📖 Read Full Thesis →

                                        SDR
                                        RF Sensing
                                        Machine Learning
                                        Signal Processing
                                    

2019 - 2022

Bachelor of Science in Electrical and Computer Engineering

Mississippi State University Starkville, MS

Academic Focus

I was deeply involved with FPGA and digital design coursework alongside embedded systems labs that translated HDL theory into practical, board-level projects.

                                        FPGA Design
                                        Digital Systems
                                        Embedded Systems
                                    

Advanced Coursework

Specialized Technical Training

💻

FPGA & Digital Design

Verilog for Digital System Design
Digital System Design

🖥️

Computer Systems & Architecture

Computer Architecture (MIPS)
Embedded System Design

🤖

Advanced Topics

Machine Learning and Artificial Intelligence
Sensor Processing for Autonomous Vehicles

Certifications

Professional Credentials & Technical Training

Featured Certifications

The Fundamentals of RDMA Programming New

NVIDIA Deep Learning Institute

September 2025 • Credential ID: 14143

View Certificate (PDF) →

Jenkins: Beginner To Pro New

AMD Learning (Udemy)

September 2025

| External Link

Verilog HDL: VLSI Hardware Design Comprehensive Masterclass

AMD Learning (Udemy)

Completed

| External Link

Linux Device Drivers

LinkedIn Learning

Completed

| External Link

Embedded Linux using Yocto

AMD Learning (Udemy)

Completed

| External Link

LPIC-2 Linux Engineer (201-450) Cert Prep

LinkedIn Learning

Completed

| External Link →

View Additional Certifications ▼

Projects

Open-source FPGA reference designs and hardware projects spanning high-speed networking, embedded systems, and robotics.

⚡ FEATURED PROJECT

⚡

DECEMBER 2025 • R&D INITIATIVE

72ns Gateway: A Versal ACAP HFT Accelerator

Nanosecond-Latency Network Processing on FPGA

Personal R&D exploration into sub-100ns packet processing on Xilinx Versal ACAP. Implements a complete hardware network stack: UDP filtering at wire speed, clock domain crossing with Gray code synchronizers, and protocol parsing for NASDAQ TotalView-ITCH 5.0 market data feeds. Demonstrates mastery of heterogeneous computing, metastability prevention, and low-latency architecture design. Target latency: 72ns (9 clock cycles @ 125 MHz).

72ns

Target Latency

125 MHz

Clock Frequency

1 Gbps

Throughput

42 Bytes

Header Stripped

Versal VCK190 UDP Filter RTL Async FIFO CDC Gray Code Sync NASDAQ ITCH 5.0 MoldUDP64 AXI Stream Vivado 2024.2

⚡ View Full Technical Documentation

🤖 FEATURED PROJECT

🤖

2024–2025 • PRODUCTION SYSTEM

Social Media Automation Engine

Temporal-Orchestrated AI Content Pipeline — Script to Published Video, Zero Human Typing

A 24,700-line Python system that autonomously discovers trending topics, generates scripts via multi-provider LLM orchestration (GPT-4o, DeepSeek, Claude), renders broadcast-quality vertical videos with FFmpeg compositing (karaoke captions, code blocks, Mermaid diagrams), and publishes to 4 platforms. Orchestrated by Temporal durable workflows with 55 activities, 5 QA gates, cascading fallback chains, and a signal-based human-in-the-loop approval via Telegram. Self-learning intelligence layer feeds performance data back into content generation. Runs on a local GPU server at $0/month.

24,700

Lines of Code

Temporal Workflows

Activities

$0/mo

Infrastructure Cost

Python 3.11 Temporal.io GPT-4o / DeepSeek FFmpeg Docker Compose FastAPI + HTMX Whisper / XTTS ComfyUI / FLUX

🤖 View Project Overview 🏗️ Architecture Deep-Dive

🧠 FEATURED PROJECT

🧠

2024–2025 • PRIVATE INFRASTRUCTURE

Cognitive Silo: Private AI Infrastructure

15 Docker Services · 12 AI Models · 48 GB VRAM · $0/Month Self-Hosted AI Stack

A single docker compose up deploys LLMs, voice cloning, image generation, video generation, music generation, and persistent AI memory behind a unified OpenAI-compatible gateway. Runs on an AMD Radeon PRO W7900 (48 GB VRAM, ROCm 6.0) with VRAM budget management, init container pattern for idempotent deployments, LiteLLM fallback routing to GPT-4o, and a 544-line interactive setup wizard. The infrastructure layer that powers the SMA pipeline and all local AI workloads.

Docker Services

AI Models

48 GB

VRAM Managed

$0/mo

Infrastructure Cost

Docker Compose Ollama (ROCm) LiteLLM Gateway AMD W7900 48GB ComfyUI / FLUX Whisper / XTTS Qdrant + Mem0 PostgreSQL + Redis

🧠 View Project Overview 🏗️ Architecture Deep-Dive

Featured: AMD Xilinx Reference Designs (2023-Present)

2023 - PRESENT

Versal ACAP Ethernet Reference Designs

Production-ready 100G DCMAC and MRMAC Ethernet reference designs for AMD Versal VPK120, VCK190, and VPK180 boards. Features 1x100G and 4x25G configurations with full Vivado/PetaLinux support, validated for low-latency network applications.

Versal ACAP 100G DCMAC MRMAC GTM SerDes PetaLinux Vivado 2024.2

View Project

2023 - PRESENT

Zynq UltraScale+ MPSoC Ethernet

Comprehensive Ethernet reference designs for ZCU102 covering PS-GEM, PL 1G/10G configurations. Includes SGMII, 1000BASE-X, and 10GBASE-R implementations with full PetaLinux BSP integration and performance validation.

Zynq UltraScale+ 10G Ethernet AXI Ethernet GTH SerDes SGMII Vivado 2024.2

View Project

2024 - PRESENT

Asynchronous FIFO (Clock Domain Crossing)

Production-grade Verilog implementation of an asynchronous FIFO for safe data transfer across independent clock domains. Features Gray code conversion, metastability prevention, and dual-domain synchronizers. Based on Clifford E. Cummings' industry-standard design principles.

Verilog Clock Domain Crossing Gray Code Metastability Synchronizers FPGA/ASIC

View Project

2023 - PRESENT

EDA/ML Synthesis Workstation

High-performance hardware infrastructure optimized for parallel Vivado synthesis, PetaLinux embedded builds, and machine learning model development. Multi-core architecture with WSL2/Linux dual-boot for seamless EDA tool integration and cross-platform development workflows.

Multi-core Synthesis PetaLinux Builds WSL2/Linux Vivado 2024 TensorFlow/PyTorch

View Project

System Architecture & High-Performance Logic

Production-grade designs: Low-latency networks, signal integrity, and real-time systems.

APRIL - DECEMBER 2022

WRECKS - Senior Design Project

Wireless Roadside Emergency Collision Kinetic Sensor

IoT sensor system for real-time collision detection on guardrails with wireless notification capabilities. Features low-latency wireless telemetry, distributed embedded architecture, and edge computing.

Raspberry Pi Real-Time Systems LoRa Wireless Embedded Linux Signal Processing

View Project

APRIL 2022

DC-DC Buck Boost Converter Analysis

Power Electronics & Switching Topology

Deep analysis of commercial buck-boost converter topology (0.5V-30V, 4A). Includes PCB reverse engineering, inductor saturation analysis, feedback loop stability, and component characterization for high-efficiency power delivery.

Power Electronics SMPS Design Control Theory Circuit Analysis

View Analysis

FEBRUARY 2021 🏆

Autonomous Drone System for COVID Testing

NXP Semiconductor Hackster.io Bonus Prize Winner

Full-stack autonomous system integrating flight control, mission planning, and contact-free payload delivery. Demonstrates real-time navigation, sensor fusion, and embedded control systems at scale.

Real-Time Flight Control Sensor Fusion PX4 Flight Stack ROS2 Navigation Computer Vision

View Project