ZCU102 Zynq UltraScale+ Ethernet

Architecture

Zynq MPSoC Ethernet Paths

┌───────────────────────────────────────────────────┐ │ ZYNQ ULTRASCALE+ MPSoC │ │ │ │ ┌─────────────────────────────────────────────┐ │ │ │ PROCESSING SYSTEM (PS) │ │ │ │ │ │ │ │ ┌─────────┐ ┌─────────┐ ┌────────┐ │ │ │ │ │ ARM A53 │ │ Linux │ │PS-GEM │ │ │ │ │ │ Cluster │───▶│ Net │───▶│Ethernet│ │ │ │ │ └─────────┘ │ Stack │ │Controller│ │ │ │ │ └─────────┘ └────┬───┘ │ │ │ └──────────────────────────────────────┼──────┘ │ │ │ │ │ ┌──────────────────────────────────────┼──────┐ │ │ │ PROGRAMMABLE LOGIC (PL) │ │ │ │ │ │ │ │ │ │ ┌──────────┐ ┌──────────────┐ │ │ │ │ │ │AXI 1G │ │ AXI 10G │ │ │ │ │ │ │Ethernet │ │ Ethernet │ │ │ │ │ │ │Subsystem│ │ Subsystem │ │ │ │ │ │ └────┬─────┘ └──────┬───────┘ │ │ │ │ │ │ │ │ │ │ │ │ ┌────┴────┐ ┌──────┴────┐ ┌────┴───┐ │ │ │ │ │ PCS/ │ │ PCS/ │ │ SGMII │ │ │ │ │ │ PMA │ │ PMA │ │ PHY │ │ │ │ │ └────┬────┘ └──────┬────┘ └────┬───┘ │ │ │ └───────┼────────────────┼────────────┼───────┘ │ │ │ │ │ │ │ ┌───────┴────┐ ┌───────┴────┐ ┌────┴────┐ │ │ │GTH SerDes │ │GTH SerDes │ │ RGMII │ │ │ │1000BASE-X │ │10GBASE-R │ │ PHY │ │ │ └───────┬────┘ └───────┬────┘ └────┬────┘ │ │ └───────────────┼────────────┘ │ │ SFP+ / RJ45 │ └───────────────────────────────────────────────────┘

Engineering

Key Design Decisions

🔀

PS-GEM vs PL Ethernet

PS-GEM provides hardened 1G Ethernet with minimal FPGA resource usage. PL-based Ethernet enables 10G and custom MAC configurations but consumes logic resources. Reference covers both paths with trade-off analysis.

📡

SGMII / 1000BASE-X / 10GBASE-R

Three PHY-layer standards for different connectivity needs. SGMII for copper, 1000BASE-X for fiber at 1G, 10GBASE-R for 10G SFP+. Each uses different SerDes line rates and PCS configurations.

⚡

GTH Transceiver Bring-Up

ZCU102 GTH transceivers require careful reference clock selection, pre-emphasis tuning, and DFE/LPM equalization. Designs include board-specific IBERT configurations for signal integrity validation.

🐧

Linux Network Integration

PetaLinux device tree configuration for PS-GEM and PL Ethernet subsystems. Includes PHY driver binding, MDIO bus configuration, and interrupt routing for stable Linux networking.

Versal vs Zynq Comparison

Versal ACAP (100G)

• DCMAC / MRMAC hardened MACs
• GTM: 112 Gbps PAM4 SerDes
• NoC-based interconnect
• 100G single-lane capable

Zynq UltraScale+ (1G/10G)

• PS-GEM + PL soft MAC
• GTH: 16.375 Gbps NRZ SerDes
• AXI interconnect
• 10G max per lane

Stack

Technology & Tools

Component	Technology	Purpose
FPGA Platform	`Zynq UltraScale+ MPSoC`	ZCU102 evaluation board
PS Ethernet	`PS-GEM Controller`	Hardened 1G Ethernet in PS
PL 1G	`AXI 1G Ethernet Subsystem`	Soft MAC with SGMII/1000BASE-X
PL 10G	`AXI 10G Ethernet Subsystem`	10GBASE-R via GTH SerDes
Transceivers	`GTH SerDes`	16.375 Gbps NRZ high-speed serial
Design Suite	`Vivado 2023+`	RTL synthesis, P&R, bitstream
Embedded OS	`PetaLinux 2023+`	BSP, device tree, kernel config
Validation	`IBERT / iperf3`	Eye diagram + throughput testing