AMD · 2023–2025 · Public reference designs
ZCU102 Ethernet Reference Designs
Six PS- and PL-based 1G/10G Ethernet example designs for the Zynq UltraScale+ MPSoC ZCU102, which I maintained at AMD. The repository replaced application note XAPP1305 and follows a rolling release: each Vivado version gets start-of-life and end-of-life tags, so you can check out the exact design for your tools.
The six designs
| Design | What it shows |
|---|---|
ps_mio_eth_1g | PS GEM over MIO to the on-board TI DP83867 PHY, 10/100/1000BASE-T |
ps_emio_eth_1g | PS GEM over EMIO to the 1G/2.5G Ethernet PCS/PMA or SGMII IP, 1000BASE-X |
ps_emio_eth_sgmii | PS GEM over EMIO to the same IP, SGMII |
pl_eth_1g | PL 1000BASE-X with the AXI Ethernet 1G/2.5G Subsystem |
pl_eth_sgmii | PL SGMII with the AXI Ethernet 1G/2.5G Subsystem |
pl_eth_10g | PL 10GBASE-R with the AXI Ethernet 10G/25G Subsystem |
Rolling releases
Designs live in one folder per Vivado release (2023.1 through 2024.2 at the time of writing). Tags such as xilinx-v2024.1-SOL mark where a release starts, and -EOL tags keep the last state of a release after it is removed from the main branch.
git clone https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet.git
cd ZCU102-Ethernet
git checkout xilinx-v2024.1-SOL
