AMD · 2023–2025 · Public reference designs
Versal Ethernet Reference Designs
AMD's public Ethernet example designs for Versal evaluation boards, which I maintained as a Sr. Embedded Product Application Engineer: from 1G PS GEM designs up to 4×25G and 1×100G on the MRMAC and DCMAC hard IP, rebuilt for each Vivado release with build scripts, validation results and known issues.
Designs by board
| Board | Designs | Tool releases |
|---|---|---|
| VCK190 | PS GEM over MIO (10/100/1000BASE-T); PS GEM over EMIO to PCS/PMA (1000BASE-X on SFP); PL AXI 1G/2.5G Ethernet (SGMII, 2500BASE-X, RPLL); PL 10G with the 10G/25G High Speed Ethernet Subsystem; MRMAC 4×25G and 1×100G | 2020.2 to 2025.1 |
| VPK120 | MRMAC 4×25G (narrow mode); DCMAC 1×100G CAUI-4 | 2023.2, 2024.2 |
| VPK180 | MRMAC 10G/25G | 2024.2 |
| VMK180 | PL 10G with the 10G/25G High Speed Ethernet Subsystem | 2023.2 |
| VEK280 | PL AXI 1G/2.5G Ethernet over SGMII, with RPLL | 2024.1 |
Every design ships the Tcl scripts that rebuild the Vivado project and block design, its XDC constraints, and a README covering the design summary, required hardware, build steps, validation results and known issues.
Related Answer Records and guides
Alongside the designs I wrote AMD Answer Records and tutorials for the questions customers kept asking:
- MRMAC tutorial seriesAR 000036973: a Versal MRMAC 4×25G bare-metal design from scratch
- DCMAC Survival GuideAR 000039394: 100G DCMAC on the VPK120 with CAUI-4
- MRMAC Linux driverAR 000038505: resolving a block-lock issue
- 10G/25G Ethernet timing closureAR 000036641
- GTY/GTYP transceiver latencyAR 75868: TX and RX latency values (team contribution)
